Impedance calibration circuit and memory device including the same
US11502687B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 29, 2021 |
| Grant date | Nov 15, 2022 |
| Priority date | — |
| Expiry date | Jul 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2254
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An impedance calibration circuit includes a first code generation circuit connected to a first reference resistor, and configured to generate a first code for forming a resistance based on the first reference resistor, by using the first reference resistor; a second code generation circuit configured to form a resistance of a second reference resistor less than the resistance of the first reference resistor, based on the first code, and generate a second code by using the second reference resistor; and a target impedance code generation circuit configured to generate a target impedance code based on the first code, the second code, and a target impedance value, and form an impedance having the target impedance value in a termination driver connected to the impedance calibration circuit, based on the target impedance code.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.