Distributing a global counter value in a multi-socket system-on-chip complex
US11507130B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 3, 2021 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Feb 3, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/7807
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses, systems, and methods for distributing a global counter value in a multi-socket SoC complex. In exemplary aspects, an apparatus comprises a first system-on-a-chip (SoC) in a first socket and a second SoC in a second socket. The apparatus further comprises a reset circuit coupled to the first SoC and the second SoC, a reset synchronization circuit coupled to the reset circuit, the first SoC, and the second SoC, and a global counter clock signal coupled to the reset synchronization circuit, the first SoC, and the second SoC. The reset synchronization circuit is configured to generate a global counter reset signal in response to a reset signal received from the reset circuit and to distribute the global counter reset signal to the first SoC and the second SoC substantially simultaneously.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.