Pre-computation of memory core control signals
US11507498B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2020 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Sep 26, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus including a memory structure comprising non-volatile memory cells and a microcontroller. The microcontroller is configured to output Core Timing Control (CTC) signals that are used to control voltages applied in the memory structure. In one aspect, information from which the CTC signals may be generated is pre-computed and stored. This pre-computation may be performed in a power on phase of the memory system. When a request to perform a memory operation is received, the stored information may be accessed and used to generate the CTC signals to control the memory operation. Thus, considerable time and/or power is saved. Note that this time savings occurs each time the memory operation is performed. Also, power is saved due to not having to repeatedly perform the computation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.