Memory device, memory cell arrangement, and methods thereof

US11508426B1 · kind B1 · utility

Assignee

• Ferroelectric Memory GmbH · DE

Inventor

• Johannes Ocker · Dresden, DE

Key dates

• Filing date: Oct 26, 2021
• Grant date: Nov 22, 2022
• Expiry date: Oct 26, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C11/4091
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Various aspects relate to a memory cell arrangement including: a field-effect transistor based capacitive memory cell including a memory element, wherein a memory state of the memory element defines a first memory state of the field-effect transistor based capacitive memory cell and wherein a second memory state of the memory element defines a second memory state of the field-effect transistor based capacitive memory cell; and a memory controller configured to, in the case that a charging state of the field-effect transistor based capacitive memory cell screens an actual threshold voltage state of the field-effect transistor based capacitive memory cell, cause a destructive read operation to determine whether the field-effect transistor based capacitive memory cell was, prior to the destructive read operation, residing in the first memory state or in the second memory state.