Voltage supply circuit, memory cell arrangement, transistor arrangement, and methods thereof
US11508428B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2021 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Oct 18, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/221
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic circuit may be operated based on two or more supply voltages ramped in accordance with a digital control scheme, the digital control scheme may include ramping a voltage value of a first output voltage generated via a first digitally controlled voltage converter from a first target voltage value to a third target voltage value such that the voltage value of the first output voltage matches a second target voltage value during a first ramp interval and the third target voltage value during a second ramp interval; and ramping a voltage value of a second output voltage generated via a second digitally controlled voltage converter from the first target voltage value to the second target voltage value such that the voltage value of the second output voltage matches the second target voltage value during the first ramp interval, and the second target voltage value during the second ramp interval.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.