System in package (SiP) semiconductor package
US11508639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 2020 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Jun 30, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes an interconnect structure having a first surface and a second surface opposing the first surface, and including a redistribution pattern and a vertical connection conductor, a first semiconductor chip disposed for a first inactive surface to oppose the first surface, a second semiconductor chip disposed on the first surface of the interconnect structure and disposed for the second inactive surface to oppose the first surface; a first encapsulant encapsulating the first and second semiconductor chips, a backside wiring layer disposed on the first encapsulant, a wiring structure connecting the redistribution pattern to the backside wiring layer, a heat dissipation member disposed on the second surface and connected to the vertical connection conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.