Method and apparatus for improved circuit structure thermal reliability on printed circuit board materials
US11508669B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 30, 2019 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Mar 6, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A structure is provided that reduces the stress generated in a semiconductor device package during cooling subsequent to solder reflow operations for coupling semiconductor devices to a printed circuit board (PCB). Stress reduction is provided by coupling solder lands to metal-layer structures using traces on the PCB that are oriented approximately perpendicular to lines from an expansion neutral point associated with the package. In many cases, especially where the distribution of solder lands of the semiconductor device package are uniform, the expansion neutral point is in the center of the semiconductor device package. PCB traces having such an orientation experience reduced stress due to thermal-induced expansion and contraction as compared to traces having an orientation along a line to the expansion neutral point.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.