Semiconductor devices and methods related thereto
US11508714B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | May 26, 2020 |
| Grant date | Nov 22, 2022 |
| Priority date | — |
| Expiry date | Jan 7, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/981
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device comprising a plurality of cells comprising cells of a first group, a second group and a third group is provided. The cell of the first group comprises a first power supply wiring for supplying a first potential, is located between the two cells of the third group and separated therefrom in a row direction by a distance, and supplies the first potential to the cells of the second group via a wiring on a front-side of the substrate. At least one of the two cells of the third group comprises a second power supply wiring for supplying a second potential having a polarity is opposite the first potential or being a ground. A third power supply wiring on a backside of a substrate supplies the first potential. The first power supply wiring comprises a via coupled to the third power supply wiring.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.