Memory cell arrangement and methods thereof

US11508756B2 · kind B2 · utility

Assignee

• Ferroelectric Memory GmbH · DE

Inventors

• Menno Mennenga · Dresden, DE
• Johannes Ocker · Dresden, DE

Key dates

• Filing date: Jun 24, 2021
• Grant date: Nov 22, 2022
• Expiry date: Jun 24, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B53/40
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A memory cell arrangement is provided that may include: a plurality of electrode layers, wherein each of the plurality of electrode layers comprises a plurality of through holes, each of the plurality of through holes extending from a first surface to a second surface of a respective electrode layer; a plurality of electrode pillars, wherein each of the plurality of electrode pillars comprises a plurality of electrode portions, wherein each of the plurality of electrode portions is disposed within a corresponding one of the plurality of through holes; wherein the respective electrode layer and a respective electrode portion of the plurality of electrode portions form a first electrode and a second electrode of a capacitor and wherein at least one memory material portion is disposed in each of the plurality of through holes in a gap between the respective electrode layer and the respective electrode portion.