Compressing micro-operations in scheduler entries in a processor
US11513802B2 · kind B2 · utility
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Key dates
| Filing date | Sep 27, 2020 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Sep 27, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30181
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device includes a processor having a micro-operation queue, multiple scheduler entries, and scheduler compression logic. When a pair of micro-operations in the micro-operation queue is compressible in accordance with one or more compressibility rules, the scheduler compression logic acquires the pair of micro-operations from the micro-operation queue and stores information from both micro-operations of the pair of micro-operations into different portions in a single scheduler entry. In this way, the scheduler compression logic compresses the pair of micro-operations into the single scheduler entry.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.