Memory device capable of adjusting clock signal based on operating speed and propagation delay of command/address signal
US11514959B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 5, 2021 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Mar 5, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and apparatuses for managing clock signals at a memory device are described. A memory device or other component of a memory module or electronic system may offset a received clock signal. For example, the memory device may receive a clock signal that has a nominal speed or frequency of operation for a system, and the memory device may adjust or offset the clock signal based on other operating factors, such as the speed or frequency of other signals, physical constraints, indications received from a host device, or the like. A clock offset value may be based on propagation of, for example, command/address signaling. In some examples, a memory module may include a registering clock driver (RCD), hub, or local controller that may manage or coordinate clock offsets among or between various memory devices on the module. Clock offset values may be programmed to a mode register or registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.