Programming devices and weights in hardware
US11514981B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2021 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Jul 21, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The method includes setting conductances for corresponding non-volatile memory (NVM) devices of a cross-bar array to zero. The method further includes determining a plurality of pulse-widths for the corresponding plurality of NVM devices based on a corresponding plurality of programming errors. Additionally, the method includes programming the NVM devices using the determined pulse-widths. Also, the method includes measuring actual conductances for the corresponding NVM devices. Further, the method includes adjusting scaling factors for the corresponding NVM devices based on the actual conductances and the corresponding programming errors. Additionally, the method includes programming the corresponding NVM devices based on the determined pulse-widths and the scaling factors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.