Methods for etching a semiconductor structure and for conditioning a processing reactor
US11515196B1 · kind B1 · utility
2Cited by
2References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 13, 2021 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | May 13, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/68735
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methods for etching a semiconductor structure and for conditioning a processing reactor in which a single semiconductor structure is treated are disclosed. An engineered polycrystalline silicon surface layer is deposited on a susceptor which supports the semiconductor structure. The polycrystalline silicon surface layer may be engineered by controlling the temperature at which the layer is deposited, by grooving the polycrystalline silicon surface layer or by controlling the thickness of the polycrystalline silicon surface layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.