Semiconductor device structure having multiple gate terminals
US11515428B2 · kind B2 · utility
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2References
14Claims
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Key dates
| Filing date | Dec 23, 2020 |
| Grant date | Nov 29, 2022 |
| Priority date | — |
| Expiry date | Mar 2, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/6739
Abstract
One example provides an integrated circuit comprising a transistor including a semiconductor channel. The semiconductor channel includes three or more sub-channels, one or more nodes, each node being a junction of at least three sub-channels, and channel ends. A Schottky contact at each channel end forms a source or drain contact, and a gate contact disposed at each Schottky contact controls a barrier conductivity of the corresponding Schottky contact.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.