Lithography supports with defined burltop topography
US11520241B2 · kind B2 · utility
0Cited by
2References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 29, 2018 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Dec 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/68757
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
Methods and systems are described for reducing adhesion and controlling friction between a wafer and a wafer table during semiconductor photolithography wherein the tops of burls on the wafer table have a layer with a nanoscale topography.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.