Performance control for a memory sub-system
US11520502B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 31, 2019 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Mar 13, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7203
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods, systems, and devices for performance control for a memory sub-system are described. A memory sub-system can monitor a backend for writing data to a memory device. The memory sub-system can determine that the bandwidth of the backend satisfies one or more performance criteria that are based on performance between the memory sub-system and a host system. In some embodiments, the memory sub-system can allocate a quantity of slots of a buffer to a frontend of the memory sub-system based on determining that the bandwidth of the backend satisfies the one or more performance criteria. Slots of the buffer can be configured to receive data from the frontend for writing to the memory device by the backend.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.