High performance, high capacity memory modules and systems
US11520508B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 21, 2020 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Sep 12, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are memory modules that include address-buffer components and data-buffer components that together support wide- and narrow-data modes. The address-buffer component manages communication between a memory controller and two sets of memory components. In the wide-data mode, the address-buffer enables memory components in each set and instructs the data-buffer components to communicate full-width read and write data by combining data from or to from both sets for each memory access. In the narrow-data mode, the address-buffer enables memory components in just one of the two sets and instructs the data-buffer components to half-width read and write data with one set per memory access.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.