Data structure optimized dedicated memory caches
US11520701B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 2, 2021 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Apr 2, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/454
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and systems associated with caches are disclosed. One disclosed system includes at least one memory storing at least two data structures. The at least two data structures include a first data structure and a second data structure. The system also includes at least two caches with a first cache which caches the first data structure and a second cache which caches the second data structure. The system also includes a controller communicatively coupled to the at least two caches. The controller separately configures the first cache based on the first data structure and the second cache based on the second data structure. The system also comprises at least one processor communicatively coupled to the at least two caches. The processor accesses each of the at least two data structures using the at least two caches and during the execution of a complex computation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.