Three-dimensional memory device erase operation

US11521988B2 · kind B2 · utility

Assignee

• YANGTZE MEMORY TECHNOLOGIES CO., LTD. · CN

Inventors

• Shiyu Xia · 红钢城街道, CN
• Feng Xu · Beijing, CN
• Lei Jin · 红钢城街道, CN
• Jie Yuan · San Jose, US
• Xuezhun Xie · 红钢城街道, CN
• Wenqiang Chen · Beijing, CN

Key dates

• Filing date: Mar 26, 2021
• Grant date: Dec 6, 2022
• Expiry date: Mar 26, 2041

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C16/0483
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Implementations of the present disclosure provide 3D memory devices and methods for operating the 3D memory devices. In an example, a 3D memory device includes a plurality of memory layers and a dummy memory layer between the plurality of memory layers and a NAND memory string extending through the memory layers and the dummy memory layer. The NAND memory string includes a source, a drain, and a plurality of memory cells at intersections with the plurality of memory layers and between the source and the drain. The 3D memory device also includes a peripheral circuit configured to erase the plurality of memory cells. To erase the plurality of memory cells, the peripheral circuit includes a word line driving circuit configured to apply a positive bias voltage on the dummy memory layer.