Assembling and handling edge interconnect packaging system
US11523511B2 · kind B2 · utility
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3Claims
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Key dates
| Filing date | Feb 3, 2021 |
| Grant date | Dec 6, 2022 |
| Priority date | — |
| Expiry date | Feb 3, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49128
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A first microchip includes holes or sockets along or in a top face or surface of the first microchip and a second microchip includes nodules extending from a edge of the second microchip. The nodules of the second microchip are received in the holes or sockets along or in the top face or surface of the first microchip, whereupon the first and second microchips are positioned transverse or perpendicular to each other.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.