Pseudo-analog memory computing circuit
US11527272B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2021 |
| Grant date | Dec 13, 2022 |
| Priority date | — |
| Expiry date | Jun 23, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C13/004
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pseudo-analog memory computing circuit includes at least one input circuit, at least one output circuit and at least one pseudo-analog memory computing unit. Each pseudo-analog memory computing unit is coupled between one of the at least one input circuit and one of the at least one output circuit and has at least one weight mode. Each pseudo-analog memory computing unit generates at least first computing result for a coupled output circuit according to a weight of a selected weight mode and at least one input signals of a coupled input circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.