Memory array circuits including word line circuits for improved word line signal timing and related methods
US11527274B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 27, 2021 |
| Grant date | Dec 13, 2022 |
| Priority date | — |
| Expiry date | May 27, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory array circuits including word line circuits providing word line signal stability are disclosed. In a memory access operation, the states of word line signals on word lines in the memory rows of the memory array may be based on the states of word line latches during a first clock state of a latch clock signal. The word line latches receive address decode signals generated from a decoded memory address. An inverted delay clock circuit generates a clock pulse from the latch clock signal. The word line latches store the address decode signals during the clock pulse and generate word line signals based on the stored address decode signals. The memory address is received from an address bus. Pass-through address capture latches maximize time available to a decoder for decoding the memory address and word line latches reduce fluctuations in the address signal being propagated to the word line signals.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.