Inventor · Chapel Hill, NC, US

Chiaming Chai

28Patents
6h-index
20Co-inventors
69Inventor score

Filing activity: Sep 25, 2000 → May 27, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US6385071B1 Redundant scheme for CAMRAM memory array Physics 42 Expired
US6452822B1 Segmented match line arrangement for content addressable memory Physics 20 Expired
US6658610B1 Compilable address magnitude comparator for memory array self-testing Physics 14 Expired
US8008961B2 Adaptive clock generators, systems, and methods Electricity 12 Active
US7073112B2 Compilable address magnitude comparator for memory array self-testing Physics 10 Expired
US8638153B2 Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width Physics 8 Active
US6816396B2 Apparatus for detecting multiple hits in a CAMRAM memory array Physics 6 Expired
US7761774B2 High speed CAM lookup using stored encoded key Physics 4 Active
US8456929B2 Circuits, systems, and methods for dynamic voltage level shifting Electricity 4 Active
US7242600B2 Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground Physics 4 Expired
US7616468B2 Method and apparatus for reducing power consumption in a content addressable memory Physics 3 Active
US7586772B2 Method and apparatus for aborting content addressable memory search operations Physics 3 Active
US7961499B2 Low leakage high performance static random access memory cell using dual-technology transistors Physics 3 Active
US7564266B2 Logic state catching circuits Electricity 3 Active
US7876631B2 Self-tuning of signal path delay in circuit employing multiple voltage domains Physics 2 Active
US9007817B2 Pre-charging bitlines in a static random access memory (SRAM) prior to data access for reducing leakage power, and related systems and methods Physics 2 Active
US7952901B2 Content addressable memory Electricity 2 Active
US9911472B1 Write bitline driver for a dual voltage domain Physics 2 Active
US9548089B2 Pipelining an asynchronous memory reusing a sense amp and an output latch Physics 1 Active
US9190141B2 Circuits for voltage or current biasing static random access memory (SRAM) bitcells during SRAM reset operations, and related systems and methods Physics 1 Active
US9442675B2 Redirecting data from a defective data entry in memory to a redundant data entry prior to data access, and related systems and methods Physics 0 Active
US6556466B2 Method and structure for a CAMRAM cache memory Physics 0 Expired
US8154900B2 Method and apparatus for reducing power consumption in a content addressable memory Physics 0 Active
US8576612B2 Low leakage high performance static random access memory cell using dual-technology transistors Physics 0 Active
US11527274B1 Memory array circuits including word line circuits for improved word line signal timing and related methods Physics 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.