Multilayer circuit board manufacturing method
US11527415B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 24, 2017 |
| Grant date | Dec 13, 2022 |
| Priority date | — |
| Expiry date | Nov 24, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/81005
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is provided a method of manufacturing a multilayer wiring board including: alternately stacking wiring layers and insulating layers; stacking a reinforcing sheet having openings on one surface of the resulting multilayer laminate with a soluble adhesive layer therebetween; contacting or infiltrating the soluble adhesive layer with a liquid capable of dissolving the soluble adhesive layer through the openings to thereby dissolve or soften the soluble adhesive layer; and releasing the reinforcing sheet from the multilayer laminate at the position of the soluble adhesive layer. This method enables the multilayer wiring layer to be reinforced so as to generate no large local warpage, thereby improving the reliable connection in the multilayer wiring layer and the flatness (coplanarity) on the surface of the multilayer wiring layer. The reinforcing sheet having finished its role can be released in a significantly short time, while minimizing the stress applied to the multilayer laminate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.