Patent · US Active

Memory cell arrangements and methods thereof

US11527551B2 · kind B2 · utility

3Cited by

6References

15Claims

0Family size

Assignee

Ferroelectric Memory GmbH · DE

Inventor

Johannes Ocker · Dresden, DE

Key dates

Filing date	Oct 30, 2020
Grant date	Dec 13, 2022
Priority date	—
Expiry date	Feb 4, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH10D1/682
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A memory cell arrangement may include: a first memory cell including a first field-effect transistor structure, a first capacitive memory structure coupled to a gate of the first field-effect transistor structure, and a first capacitive lever structure coupled to the gate of the first field-effect transistor structure, and wherein a second memory cell of the plurality of memory cells includes a second field-effect transistor structure, a second capacitive memory structure coupled to a gate of the second field-effect transistor structure, and a second capacitive lever structure coupled to the gate of the second field-effect transistor structure; wherein at least one of the first capacitive memory structure and/or the second capacitive memory structure is disposed in a memory structure region between the first capacitive lever structure and the second capacitive lever structure.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.