Selecting an ith largest or a pth smallest number from a set of n m-bit numbers
US11531522B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 31, 2019 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Feb 10, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/78
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m−r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m−r−1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m−r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.