Error recovery for non-volatile memory modules
US11531601B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 30, 2019 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Dec 4, 2040 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/82
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory controller includes a command queue, a memory interface queue, at least one storage queue, and a replay control circuit. The command queue has a first input for receiving memory access commands. The memory interface queue receives commands selected from the command queue and couples to a heterogeneous memory channel which is coupled to at least one non-volatile storage class memory (SCM) module. The at least one storage queue stores memory access commands that are placed in the memory interface queue. The replay control circuit detects that an error has occurred requiring a recovery sequence, and in response to the error, initiates the recovery sequence. In the recovery sequence, the replay control circuit transmits selected memory access commands from the at least one storage queue by grouping non-volatile read commands together separately from all pending volatile reads, volatile writes, and non-volatile writes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.