Conductive feature structure including a blocking region
US11532503B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 23, 2020 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Nov 23, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76855
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Generally, the present disclosure provides example embodiments relating to conductive features, such as metal contacts, vias, lines, etc., and methods for forming those conductive features. In an embodiment, a structure includes a first dielectric layer over a substrate, a first conductive feature in the first dielectric layer, a second dielectric layer over the first dielectric layer, a second conductive feature in the second dielectric layer, and a blocking region disposed between the first conductive feature and the second conductive feature. The second conductive feature is disposed between and abutting a first sidewall of the second dielectric layer and a second sidewall of the second dielectric layer. The blocking region extends laterally at least from the first sidewall of the second dielectric layer to the second sidewall of the second dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.