Misregistration target having device-scaled features useful in measuring misregistration of semiconductor devices
US11532566B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 25, 2020 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Oct 13, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2223/54426
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A target and method for using the same in the measurement of misregistration between at least a first layer and a second layer formed on a wafer in the manufacture of functional semiconductor devices on the wafer, the functional semiconductor devices including functional device structures (FDSTs), the target including a plurality of measurement structures (MSTs), the plurality of MSTs being part of the first layer and the second layer and a plurality of device-like structures (DLSTs), the plurality of DLSTs being part of at least one of the first layer and the second layer, the DLSTs sharing at least one characteristic with the FDSTs and the MSTs not sharing the at least one characteristic with the FDSTs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.