Source/drain contact structure
US11532627B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 9, 2020 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Nov 9, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device according to the present disclosure includes a first interconnect structure, a first transistor over the first interconnect structure, a second transistor over the first transistor, and a second interconnect structure over the second transistor. The first transistor includes first nanostructures and a first source region adjoining the first nanostructures. The second transistor includes second nanostructures and a second source region adjoining the second nanostructures. The first source region is coupled to a first power rail in the first interconnect structure, and the second source region is coupled to a second power rail in the second interconnect structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.