Dual port memory cell with improved access resistance
US11532633B2 · kind B2 · utility
1Cited by
22References
20Claims
0Family size
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Key dates
| Filing date | Sep 30, 2021 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Sep 30, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure is directed to a circuit layout of a dual port static random-access-memory (SRAM) cell. The memory cell includes active regions in a substrate, with polysilicon gate electrodes on the active regions to define transistors of the memory cell. The eight transistor (8T) memory cell layout includes a reduced aspect ratio and non-polysilicon bit line discharge path routing by positioning an active region for the first port opposite an active region for the second port and consolidating power line nodes at a central portion of the memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.