Three-dimensional semiconductor memory device
US11532639B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 2020 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Jun 18, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/40
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a three-dimensional semiconductor memory device including a carbon-containing layer on a substrate, a plurality of electrode interlayer dielectric layers and a plurality of electrode layers that are alternately stacked on the carbon-containing layer, a cell vertical pattern that penetrates at least some of the electrode interlayer dielectric layers and the electrode layers, and a semiconductor pattern between the cell vertical pattern and the carbon-containing layer. The substrate includes a plurality of first grains. The semiconductor pattern includes a plurality of second grains. An average size of the second grains is less than an average size of the first grains.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.