3D memory and manufacturing process
US11532670B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2020 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Mar 12, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/8833
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.