Inventor · Meylan, FR

Francois Andrieu

29Patents
2h-index
39Co-inventors
57Inventor score

Filing activity: May 13, 1991 → Jul 21, 2021

Most-cited inventions

PatentTitleAreaCited byStatus
US5140289A Combined microwave and optic rotary joint Physics 26 Expired
US9520330B2 Integrated circuit comprising PMOS transistors with different voltage thresholds Electricity 3 Active
US9214515B2 Method for making a semiconductor structure with a buried ground plane Electricity 1 Active
US8809964B2 Method of adjusting the threshold voltage of a transistor by a buried trapping layer Electricity 1 Active
US9558957B2 Method for manufacturing a substrate provided with different active areas and with planar and three-dimensional transistors Electricity 1 Active
US8853023B2 Method for stressing a thin pattern and transistor fabrication method incorporating said method Electricity 1 Active
US10263110B2 Method of forming strained MOS transistors Electricity 1 Active
US7820523B2 Fabrication of active areas of different natures directly onto an insulator: application to the single or double gate MOS transistor Emerging Cross-Sectional Technologies 1 Active
US9985029B2 Integrated circuit with NMOS and PMOS transistors having different threshold voltages through channel doping and gate material work function schemes Electricity 1 Active
US10418486B2 Integrated circuit chip with strained NMOS and PMOS transistors Electricity 0 Active
US10504897B2 Integrated circuit comprising balanced cells at the active Electricity 0 Active
US11810789B2 Method of fabricating a semiconductor substrate having a stressed semiconductor region Electricity 0 Active
US9514996B2 Process for fabricating SOI transistors for an increased integration density Electricity 0 Active
US9876032B2 Method of manufacturing a device with MOS transistors Electricity 0 Active
US11139209B2 3D circuit provided with mesa isolation for the ground plane zone Electricity 0 Active
US8501588B2 Method for making a semiconductor structure with a buried ground plane Electricity 0 Active
US10651202B2 3D circuit transistors with flipped gate Electricity 0 Active
US11653506B2 Resistive 3D memory Electricity 0 Active
US11889704B2 Device comprising wrap-gate transistors and method of manufacturing such a device Electricity 0 Active
US11024544B2 Assembly for 3D circuit with superposed transistor levels Electricity 0 Active
US10446548B2 Integrated circuit including balanced cells limiting an active area Electricity 0 Active
US10777680B2 Integrated circuit chip with strained NMOS and PMOS transistors Electricity 0 Active
US11888007B2 Image sensor formed in sequential 3D technology Electricity 0 Active
US11532670B2 3D memory and manufacturing process Electricity 0 Active
US11011425B2 Production of a 3D circuit with upper level transistor provided with a gate dielectric derived from a substrate transfer Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.