Method of fabricating array substrate, array substrate, and display apparatus
US11532679B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 15, 2019 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Jan 10, 2040 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10K59/1201
Abstract
A method of fabricating an array substrate is provided. The method includes forming a plurality of first thin film transistors on a base substrate, a respective one of the plurality of first thin film transistors formed to include a first active layer, a first gate electrode, a first source electrode and a first drain electrode; and forming a plurality of second thin film transistors on the base substrate, a respective one of the plurality of second thin film transistors formed to include a second active layer, a second gate electrode, a second source electrode and a second drain electrode. Forming the first source electrode includes forming a first source sub-layer and forming a second source sub-layer in separate patterning steps. Forming the first drain electrode includes forming a first drain sub-layer and forming a second drain sub-layer in separate patterning steps.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.