Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures

US11532706B2 · kind B2 · utility

Assignee

• Intel Corporation · US

Inventors

• Cory Bomberger · Portland, US
• Anand S. Murthy · Beaverton, US
• Susmita Ghose · Mountain View, US
• Siddharth Chouksey · Portland, US

Key dates

• Filing date: Mar 29, 2019
• Grant date: Dec 20, 2022
• Expiry date: Apr 18, 2041

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/83
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, and methods of fabricating gate-all-around integrated circuit structures having embedded GeSnB source or drain structures, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal nanowires above a fin, the fin including a defect modification layer on a first semiconductor layer, and a second semiconductor layer on the defect modification layer. A gate stack is around the vertical arrangement of horizontal nanowires. A first epitaxial source or drain structure is at a first end of the vertical arrangement of horizontal nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal nanowires.