Semiconductor device having vertical DMOS and manufacturing method thereof
US11532741B2 · kind B2 · utility
2Cited by
1References
28Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 15, 2021 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Jul 4, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device includes a substrate, a buried doped layer formed on the substrate, a trench gate formed on the buried doped layer, a source region formed adjacent the trench gate, an interlayer dielectric layer formed on the trench gate and the source region, a source contact plug formed to extend and connect to the source region, and a drain contact plug, extending and connecting to the buried doped layer, formed deeper than the source contact plug.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.