Multi-bit memory storage device and method of operating same
US11532746B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2021 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Feb 25, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/689
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric field-effect transistor (FeFET) configured as a multi-bit storage device, the FeFET including: a semiconductor substrate that has a source region in the semiconductor substrate, and a drain region in the semiconductor substrate; a gate stack over the semiconductor substrate, with the source region and the drain region extending to opposite sides of the gate stack, the gate stack including a ferroelectric layer over the semiconductor substrate, and a gate region over the ferroelectric layer. The transistor also includes first and second ends of the ferroelectric layer which are proximal correspondingly to the source and drain regions. The ferroelectric layer includes dipoles. A first set of dipoles at the first end of the ferroelectric layer has a first polarization. A second set of dipoles at the second end of the ferroelectric layer has a second polarization, the second polarization being substantially opposite of the first polarization.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.