Non-volatile memory device with reduced area
US11532752B2 · kind B2 · utility
3Cited by
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20Claims
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Key dates
| Filing date | Apr 16, 2021 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Apr 20, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/5252
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a substrate, a semiconductor fin over the substrate and extending in a first direction, and a first gate electrode and a second gate electrode over the substrate and extending in a second direction. The semiconductor fin extends through the second gate electrode and terminates on the first gate electrode at one end. The memory device further includes a first conductive via over and electrically coupled to the first gate electrode. The one end of the semiconductor fin is surrounded by the first gate electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.