Ultra-low power adaptively reconfigurable system
US11533055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 29, 2019 |
| Grant date | Dec 20, 2022 |
| Priority date | — |
| Expiry date | Jul 21, 2039 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Implementations disclosed describe a programmable analog subsystem (PASS) having a plurality of reconfigurable analog circuits. The PASS may be coupled to an input/output device to receive an input signal and to an interface to communicate data with a central processing unit. In a first PASS configuration, with the plurality of reconfigurable analog circuits having a first configuration setting, the PASS may process the input signal through the plurality of reconfigurable analog circuits to generate a first output value based on the input signal. Responsive to the first output value, the PASS may reconfigure the plurality of reconfigurable analog circuits into a second PASS configuration having a second configuration setting, such that the second configuration setting is different than the first configuration setting.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.