Patent · US Active

Hardware mechanisms for link encryption

US11533170B2 · kind B2 · utility

2Cited by

3References

23Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Reouven Elbaz · Portland, US
Hooi Kar Loo · Bayan Lepas, MY
Poh Thiam Teoh · Bandar Baru Sungai Buloh, MY
Su Wei Lim · Klang, MY
Patrick Maloney · Mentor, US
Santosh Ghosh · Hillsboro, US

Key dates

Filing date	Mar 28, 2019
Grant date	Dec 20, 2022
Priority date	—
Expiry date	Mar 30, 2041

Classification

Technology area (CPC H)Electricity
CPC primaryH04L2209/122
WIPO fieldDigital communication
WIPO sectorElectrical engineering

Abstract

Methods, systems, and apparatuses associated with hardware mechanisms for link encryption are disclosed. In various embodiments, an interconnect interface is coupled to a processor core to interconnect a peripheral device to the processor core via a link established between the peripheral device and the interconnect interface. The interconnect interface is to select a cryptographic engine of a plurality of cryptographic engines instantiated in the interconnect interface for the link. The cryptographic engine is to symmetrically encrypt data to be transmitted through the link. In more specific embodiments, each of the plurality of cryptographic engines is instantiated for one of a request type on the link, a virtual channel on the link, or a request type within a virtual channel on the link.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.