Host-based error correction
US11537464B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 2019 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Dec 19, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/35
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Systems, apparatuses, and methods related to host-based error correction are described. Error correction operations can be performed on a host computing system as opposed to on a memory system. For instance, data containing erroneous bits can be transferred from a memory system to a host computing system and error correction operations can be performed using circuitry resident on the host computing system. In an example, a method can include receiving, by a host computing system, data that comprises a plurality of uncorrected bits from a memory system coupleable to the host computing system, determining an acceptable error range for the data based at least in part on an application associated with the data, and performing, using error correction logic resident on the host computing system, an initial error correction operation on the data based at least in part on the acceptable error range.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.