Asynchronous power loss recovery for memory devices
US11537512B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 21, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Oct 21, 2041 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to maintain a logical-to-physical (L2P) table, wherein a region of the L2P table is cached in a volatile memory; maintain a write count reflecting a number of bytes written to the memory device; maintain a cache miss count reflecting a number of cache misses with respect to a cache of the L2P table; responsive to determining that a value of a predetermined function of the write count and the cache miss count exceeds a threshold value, copy the region of the L2P table to a non-volatile memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.