System and method for compact neural network modeling of transistors
US11537841B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 3, 2019 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Oct 8, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/105
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for generating a model of a transistor includes: initializing hyper-parameters; training the neural network in accordance with the hyper-parameters and training data relating transistor input state values to transistor output state values to compute neural network parameters; determining whether the transistor output state values of the training data match an output of the neural network; porting the neural network to a circuit simulation code to generate a ported neural network; simulating a test circuit using the ported neural network to simulate behavior of a transistor of the test circuit to generate simulation output; determining whether a turnaround time of the generation of the simulation output is satisfactory; in response to determining that the turnaround time is unsatisfactory, re-training the neural network based on updated hyper-parameters; and in response to determining that the turnaround time is satisfactory, outputting the ported neural network as the model of the transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.