Apparatus and methods for fractional synchronization using direct digital frequency synthesis
US11538511B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 11, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Jul 29, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Described are apparatus and methods for fractional synchronization using direct digital frequency synthesis (DDFS). A DDFS device includes a memory with N address spaces, a write port circuit configured to sequentially write a digital desired pattern into the N address spaces, a read port circuit configured to readout the digital desired pattern from the N address spaces using continuous sequential automatic addressing from 0 to N−1 at a memory operating frequency clock, where the memory operating frequency clock is based on a sampling frequency clock used for high-speed data processing, and an analog signal processing circuit configured to process a readout digital desired pattern into an analog representation; and output a synthesized frequency clock from the analog representation to a digital core, where the synthesized frequency clock is fractionally synchronized with the sampling frequency clock.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.