Silicon over insulator two-transistor two-resistor in-series resistive memory cell
US11538524B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 12, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Jul 12, 2041 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/79
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A resistive random-access memory (ReRAM) cell formed on a silicon over insulator substrate (SOI) is provided. The ReRAM includes a SOI substrate, a first MOSFET and a second MOSFET, each of which having a drain port, a gate port, a source port, and a bulk port. The drain port of the second MOSFET is connected to the source port of the first MOSFET; a first resistive element and a second resistive element, each having a first port and a second port, wherein the first ports of both resistive elements are connected to the drain of the first MOSFET; a first word line and a second word line connected to the gate port of the first MOSFET and the second MOSFET, respectively; and the state of the ReRAM cell is determined upon applying a predefined potential.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.