Systems and methods for read error recovery
US11538547B2 · kind B2 · utility
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3References
20Claims
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Key dates
| Filing date | Nov 10, 2020 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Nov 10, 2040 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments provide a scheme for determining the order of read threshold voltages used in a read error recovery operation for a memory system. A controller performs one or more read operations on a memory device using one or more read voltages among a plurality of read voltages in a set order. The controller detects a successful read operation among the one or more read operations. The controller determines one or more credits for the one or more read voltages, respectively, in response to the detected successful read operation. The controller updates the set order based on the determined credits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.