Packaging method, panel assembly, wafer package and chip package
US11538695B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Dec 5, 2019 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Dec 5, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2224/96
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The embodiments of the present disclosure relate to a packaging method, a panel assembly, a wafer package and a chip package. The semiconductor device packaging method includes: providing at least one wafer including a first surface and a second surface opposite to each other and a side surface connecting the first surface and the second surface, the first surface being an active surface; forming a connection portion on the side surface of the at least one wafer around the wafer, the wafer and the connection portion forming a panel assembly, the connection portion includes a third surface on the same side of the first surface of the wafer and a fourth surface on the same side as the second surface of the wafer, the third surface and the first surface forming a to-be-processed surface of the panel assembly; and forming a first dielectric layer on the first surface of the wafer. The packaging method of the embodiments of the present disclosure may improve packaging efficiency and utilization of a wafer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.