Semiconductor package
US11538737B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2020 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Jun 3, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3511
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a redistribution substrate having a first redistribution layer, a semiconductor chip on the redistribution substrate and connected to the first redistribution layer, a vertical connection conductor on the redistribution substrate and electrically connected to the semiconductor chip through the first redistribution layer, a core member having a first through-hole accommodating the semiconductor chip and a second through-hole accommodating the vertical connection conductor, and an encapsulant covering at least a portion of each of the semiconductor chip, the vertical connection conductor, and the core member, the encapsulant filling the first and second through-holes, wherein the vertical connection conductor has a cross-sectional shape with a side surface tapered to have a width of a lower surface thereof is narrower than a width of an upper surface thereof, and the first and second through-holes have a cross-sectional shape tapered in a direction opposite to the vertical connection conductor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.