Semiconductor package
US11538801B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2021 |
| Grant date | Dec 27, 2022 |
| Priority date | — |
| Expiry date | Apr 16, 2041 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19106
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a first substrate that includes a first trench on a recessed portion of a bottom surface of the first substrate and a first through hole extending through the first substrate to the first trench, a first semiconductor chip on the first substrate, a first capacitor chip in the first trench and on the first substrate, and a first molding layer on the first substrate and covering the first semiconductor chip. The first molding layer includes a first part that extends parallel to a top surface of the first substrate, a second part connected to the first part and extending vertically in the first through hole, and a third part connected to the second part and surrounding the first capacitor chip. A bottom surface of the third part is coplanar with the bottom surface of the first substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.